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00014 #ifndef FAUDES_TP_TPARALLEL_H
00015 #define FAUDES_TP_TPARALLEL_H
00016
00017 #include "tp_tgenerator.h"
00018
00019 namespace faudes {
00020
00021
00022
00023 #define TEMP template < \
00024 class GlobalAttr1, class StateAttr1, class EventAttr1, class TransAttr1, \
00025 class GlobalAttr2, class StateAttr2, class EventAttr2, class TransAttr2, \
00026 class GlobalAttrR, class StateAttrR, class EventAttrR, class TransAttrR >
00027
00028 #define TGEN1 TtGenerator<GlobalAttr1,StateAttr1,EventAttr1,TransAttr1>
00029 #define TGEN2 TtGenerator<GlobalAttr2,StateAttr2,EventAttr2,TransAttr2>
00030 #define TGENR TtGenerator<GlobalAttrR,StateAttrR,EventAttrR,TransAttrR>
00031
00032
00050 TEMP void TParallel(const TGEN1& rGen1, const TGEN2& rGen2, TGENR& rResGen);
00051
00052
00073 TEMP void TParallel(
00074 const TGEN1& rGen1, const TGEN2& rGen2,
00075 std::map< std::pair<Idx,Idx>, Idx>& rReverseCompositionMap,
00076 TGENR& rResGen);
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090 TEMP void TParallel(const TGEN1& rGen1, const TGEN2& rGen2, TGENR& rResGen) {
00091
00092 rResGen.Clear();
00093
00094 std::map< std::pair<Idx,Idx>, Idx> rcmap;
00095 TParallel(rGen1, rGen2, rcmap, rResGen);
00096 if (rGen1.StateNamesEnabled() && rGen2.StateNamesEnabled())
00097 SetComposedStateNames(rGen1, rGen2, rcmap, rResGen);
00098 }
00099
00100
00101
00102 TEMP void TParallel(
00103 const TGEN1& rGen1, const TGEN2& rGen2,
00104 std::map< std::pair<Idx,Idx>, Idx>& rReverseCompositionMap,
00105 TGENR& rResGen)
00106 {
00107 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << ")");
00108
00109
00110 Parallel( rGen1, rGen2, rReverseCompositionMap, rResGen);
00111
00112 ClockSet clocks12;
00113 clocks12.InsertSet(rGen1.Clocks());
00114 clocks12.InsertSet(rGen2.Clocks());
00115 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): clocks:" << clocks12.ToString());
00116 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): clocks:" << rGen1.Clocks().ToString());
00117 rResGen.InjectClocks(clocks12);
00118
00119 std::map< std::pair<Idx,Idx>, Idx>::const_iterator rcit;
00120 for(rcit=rReverseCompositionMap.begin(); rcit!=rReverseCompositionMap.end(); rcit++) {
00121 Idx x1=rcit->first.first;
00122 Idx x2=rcit->first.second;
00123 Idx x12=rcit->second;
00124 if(!rResGen.ExistsState(x12)) continue;
00125 TimeConstraint invariant12;
00126 invariant12 << rGen1.Invariant(x1);
00127 invariant12 << rGen2.Invariant(x2);
00128 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): invariant " << x1 << "|" << x2
00129 << " :" << invariant12.ToString());
00130 rResGen.Invariant(x12,invariant12);
00131 }
00132
00133 std::map< Idx, std::pair<Idx,Idx> > compositionmap;
00134 for(rcit=rReverseCompositionMap.begin(); rcit!=rReverseCompositionMap.end(); rcit++)
00135 compositionmap[rcit->second]=rcit->first;
00136
00137 TransSet::Iterator tit;
00138 for(tit=rResGen.TransRelBegin(); tit!=rResGen.TransRelEnd(); tit++) {
00139
00140 TimeConstraint guard;
00141 ClockSet resets;
00142
00143 if(rGen1.ExistsEvent(tit->Ev)) {
00144 Transition t1;
00145 t1.X1=compositionmap[tit->X1].first;
00146 t1.Ev=tit->Ev;
00147 t1.X2=compositionmap[tit->X2].first;
00148 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): guard/resets in Gen1 for " << t1.Str());
00149 guard.Insert(rGen1.Guard(t1));
00150 resets.InsertSet(rGen1.Resets(t1));
00151 }
00152
00153 if(rGen2.ExistsEvent(tit->Ev)) {
00154 Transition t2;
00155 t2.X1=compositionmap[tit->X1].second;
00156 t2.Ev=tit->Ev;
00157 t2.X2=compositionmap[tit->X2].second;
00158 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): guard/resets in Gen2 for " << t2.Str());
00159 guard.Insert(rGen2.Guard(t2));
00160 resets.InsertSet(rGen2.Resets(t2));
00161 }
00162 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): guard " << tit->Str()
00163 << " :" << guard.ToString());
00164 rResGen.Guard(*tit,guard);
00165 FD_DF("TParallel(" << &rGen1 << "," << &rGen2 << "): resets " << tit->Str()
00166 << " :" << resets.ToString());
00167 rResGen.Resets(*tit,resets);
00168 }
00169 FD_DF("TParallel: done ");
00170 }
00171
00172
00173
00174
00175 #undef TEMP
00176 #undef GEN1
00177 #undef GEN2
00178 #undef GENR
00179
00180
00181 }
00182
00183 #endif
00184